Automatic test equipment (ATE) plays a significant role in the manufacture of semiconductor devices. Manufacturers generally use automatic test equipment--or "testers"--to verify the operation of semiconductor devices at the wafer and packaged device stages of semiconductor manufacturing processes. By testing semiconductor devices at these stages, manufacturers are able to reject defective devices early in the manufacturing process. Early detection of faults eliminates costs that would otherwise be incurred by processing defective parts, and thus reduces the overall costs of manufacturing. Manufacturers also use ATE to grade various specifications of devices. Devices can be tested and categorized within different bins that correspond to different levels of performance in significant areas, for example, speed. Parts can then be labeled and sold according to their levels of performance.
A tester generally includes a host computer that runs software for controlling various tests of the semiconductor devices. The software prescribes signal characteristics for applying stimuli to the DUT (device under test) and for sampling responses from the DUT. A pattern generator translates the signal characteristics into timing signals. Specialized circuitry called pin electronics then converts the timing signals into actual stimuli and timing windows.
Pin electronics are generally grouped among different circuits of the ATE called "channels." The channels provide a signal interface between the tester and the DUT. Each channel typically includes a driver circuit and a detector circuit. The present invention pertains to a new type of detector circuit for use in pin electronics channels of ATE.
Detector circuits are used in automatic test equipment to sample digital signals generated by a device under test. FIG. 1 illustrates a highly simplified ATE system. As shown in FIG. 1, a host computer 118 runs a test program for testing a DUT 122 via a plurality of digital channels, shown generally as channels 110a-110e.
Each of the plurality of channels 110a-110e has an I/O terminal, respectively 120a-120e, that can be coupled to the DUT 122. Each channel typically includes a driver circuit 112, a detector circuit 114, and channel overhead circuitry 116. The channel overhead circuitry 116 typically includes digital-to-analog converters (DACs) for establishing drive levels for the driver circuit 112 and for establishing detect levels for the detector circuit 114. The channel overhead circuitry 116 typically also controls the driver circuit 112 to apply signal edges at precise instants in time, and controls the detector circuit 114 to sample input signals at precise instants in time. The channel overhead circuitry 116 may also include memory for storing digital patterns to be applied to the DUT by the driver circuit 112 and for storing digital states sampled by the detector circuit 114.
Traditionally, the role of detector circuits in ATE has been for sampling single-ended signals, i.e., for determining whether a single-ended digital signal is in a high logic state, a low logic state, or a logic state between high and low (a "between" state). We have recognized, however, that there is also a need for sampling differential signals. In contrast with single-ended signals, which provide one signal for conveying a digital logic state with reference to a digital ground, differential signals convey digital logic states as differences between two signals, neither one of which is digital ground.
Rapidly developing technologies such as IEEE 1324 (Firewire) and LVDS (Low Voltage Differential Signaling) extensively use differential digital communication. These technologies impose strict specifications on differential signals. A need has arisen, therefore, for testing the specifications of differential digital signals using ATE.